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PD - 95278
IRF7475PBF
HEXFET(R) Power MOSFET
Applications l High Frequency Point-of-Load Synchronous Buck Converter for Applications in Networking & Computing Systems. l Lead-Free Benefits l Very Low RDS(on) at 4.5V VGS l Ultra-Low Gate Impedance l Fully Characterized Avalanche Voltage and Current
VDSS
12V
RDS(on) max
15m:@VGS = 4.5V
A A D D D D
Qg
19nC
S S S G
1
8 7
2
3
6
4
5
Top View
SO-8
Absolute Maximum Ratings
Parameter
VDS VGS ID @ TA = 25C ID @ TA = 100C IDM PD @TA = 25C PD @TA = 70C TJ TSTG Drain-to-Source Voltage Gate-to-Source Voltage Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current
Max.
12 12 11 7.0 88 2.5 1.6 0.02 -55 to + 150
Units
V
g Power Dissipation g
Power Dissipation
c
A W
Linear Derating Factor Operating Junction and Storage Temperature Range
W/C C
Thermal Resistance
Parameter
RJL RJA Junction-to-Drain Lead Junction-to-Ambient
Typ.
--- ---
Max.
20 50
Units
C/W
f
Notes through are on page 10
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1
09/21/04
IRF7475PBF
Static @ TJ = 25C (unless otherwise specified)
Parameter
BVDSS VDSS/TJ RDS(on) VGS(th) VGS(th) IDSS IGSS gfs Qg Qgs1 Qgs2 Qgd Qgodr Qsw Qoss td(on) tr td(off) tf Ciss Coss Crss Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Gate Threshold Voltage Coefficient Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Forward Transconductance Total Gate Charge Pre-Vth Gate-to-Source Charge Post-Vth Gate-to-Source Charge Gate-to-Drain Charge Gate Charge Overdrive Switch Charge (Qgs2 + Qgd) Output Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance
Min. Typ. Max. Units
12 --- --- --- 0.6 --- --- --- --- --- 22 --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- 0.014 11.5 20 --- 3.2 --- --- --- --- --- 13 2.6 1.5 3.9 5.0 5.4 17 7.5 33 13 7.5 1590 1310 260 --- --- 15 50 2.0 --- 100 250 200 -200 --- 19 --- --- --- --- --- --- --- --- --- --- --- --- --- pF VGS = 0V VDS = 6.0V ns nC nC VDS = 6.0V VGS = 4.5V ID = 7.0A S nA V mV/C A V m
Conditions
VGS = 0V, ID = 250A VGS = 4.5V, ID = 8.8A VGS = 2.8V, ID = 5.5A
V/C Reference to 25C, ID = 1mA
f f
VDS = VGS, ID = 250A VDS = 9.6V, VGS = 0V VDS = 9.6V, VGS = 0V, TJ = 125C VGS = 12V VGS = -12V VDS = 6.0V, ID = 8.8A
See Fig. 16 VDS = 10V, VGS = 0V VDD = 6.0V, VGS = 4.5V ID = 8.8A Clamped Inductive Load
f
= 1.0MHz
Avalanche Characteristics
EAS IAR EAR Parameter Single Pulse Avalanche Energy Avalanche Current
dh
Typ. --- --- ---
Max. 180 8.8 0.25
Units mJ A mJ
Repetitive Avalanche Energy
--- --- --- --- --- --- --- --- 42 44
Diode Characteristics
Parameter
IS ISM VSD trr Qrr ton Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode)Ah Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge Forward Turn-On Time
Min. Typ. Max. Units
11 A 88 1.3 63 66 V ns nC
Conditions
MOSFET symbol showing the integral reverse
G D
S p-n junction diode. TJ = 25C, IS = 8.8A, VGS = 0V
f
TJ = 25C, IF = 8.8A, VDD = 10V di/dt = 100A/s
f
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
2
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IRF7475PBF
100 VGS TOP 10V 8.0V 4.5V 3.5V 3.0V 2.8V 2.25V BOTTOM 2.0V
100 VGS 10V 8.0V 4.5V 3.5V 3.0V 2.8V 2.25V BOTTOM 2.0V TOP
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
10
10
2.0V
1
2.0V
1
20s PULSE WIDTH TJ = 25C
0.1 0.1
0.1
20s PULSE WIDTH TJ = 150C
1 10 100
1
10
100
0.1
VDS, Drain-to-Source Voltage (V)
VDS, Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
100
2.0
RDS(on), Drain-to-Source On Resistance
ID = 11A VGS = 4.5V
ID, Drain-to-Source Current (A)
1.5
10
TJ = 150C
(Normalized)
1.0
TJ = 25C
0.5
VDS = 10V 20s PULSE WIDTH
1 1 2 3 4 5
0.0 -60 -40 -20 0 20 40 60 80 100 120 140 160
VGS, Gate-to-Source Voltage
TJ, Junction Temperature (C)
Fig 3. Typical Transfer Characteristics
Fig 4. Normalized On-Resistance Vs. Temperature
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IRF7475PBF
10000
VGS, Gate-to-Source Voltage (V)
VGS = 0V, f = 1 MHZ Ciss = Cgs + Cgd, Cds SHORTED Crss = Cgd Coss = Cds + Cgd
6
ID = 7.0A VDS = 12V VDS = 6.0V
5
C, Capacitance (pF)
4
Ciss
1000
Coss
3
2
1
Crss
100 1 10 100
0 0 5 10 15 20
VDS, Drain-to-Source voltage (V)
QG, Total Gate Charge (nC)
Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage
100
1000
OPERATION IN THIS AREA LIMITED BY RDS(on)
ISD, Reverse Drain Current (A) TJ = 150C
10
ID, Drain-to-Source Current (A)
100
10sec
10
1msec 10msec
1
TJ = 25C
1
VGS = 0V
0.1 0.0 0.5 1.0 1.5 2.0
TC = 25C TJ = 150C Single Pulse
0.1 0.1 1 10 100
VSD, Source-to-Drain Voltage (V)
VDS, Drain-to-Source Voltage (V)
Fig 7. Typical Source-Drain Diode Forward Voltage
Fig 8. Maximum Safe Operating Area
4
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IRF7475PBF
12
1.6
VGS(th), Gate Threshold Voltage (V)
ID , Drain Current (A)
9
1.4
ID = 250A
1.2
6
3
1.0
0
0.8
25
50
75
100
125
150
-75
-50
-25
0
25
50
75
100
125
150
TC , Case Temperature ( C)
TJ, Temperature (C)
Fig 9. Maximum Drain Current Vs. Case Temperature
Fig 10. Threshold Voltage Vs. Temperature
100
Thermal Response (Z thJA )
D = 0.50 0.20 0.10 0.05 0.02 0.01 PDM t1 t2 SINGLE PULSE (THERMAL RESPONSE) 0.1 0.00001 0.0001 0.001 0.01 0.1 Notes: 1. Duty factor D = t 1 / t 2 2. Peak T J = P DM x Z thJA + TA 1 10 100
10
1
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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IRF7475PBF
500
EAS , Single Pulse Avalanche Energy (mJ)
15V
VDS
L
DRIVER
400
ID 3.9A 7.0A BOTTOM 8.8A TOP
RG
VGS 20V
D.U.T
IAS tp
+ V - DD
300
A
0.01
200
Fig 12a. Unclamped Inductive Test Circuit
V(BR)DSS tp
100
0 25 50 75 100 125 150
Starting T J , Junction Temperature (C)
Fig 12c. Maximum Avalanche Energy Vs. Drain Current
I AS
V DS VGS RG
Current Regulator Same Type as D.U.T.
RD
Fig 12b. Unclamped Inductive Waveforms
D.U.T.
+
-VDD
VGS
Pulse Width 1 s Duty Factor 0.1 %
50K 12V .2F .3F
Fig 14a. Switching Time Test Circuit
D.U.T. + V - DS
VDS 90%
VGS
3mA
IG
ID
10% VGS
td(on) tr t d(off) tf
Current Sampling Resistors
Fig 13. Gate Charge Test Circuit
Fig 14b. Switching Time Waveforms
6
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IRF7475PBF
D.U.T
Driver Gate Drive
+
P.W.
Period
D=
P.W. Period VGS=10V
+
Circuit Layout Considerations * Low Stray Inductance * Ground Plane * Low Leakage Inductance Current Transformer
*
D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt
-
+
RG
* * * * dv/dt controlled by RG Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test
V DD
VDD
+ -
Re-Applied Voltage Inductor Curent
Body Diode
Forward Drop
Ripple 5%
ISD
* VGS = 5V for Logic Level Devices Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET(R) Power MOSFETs
Id Vds Vgs
Vgs(th)
Qgs1 Qgs2
Qgd
Qgodr
Fig 16. Gate Charge Waveform
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IRF7475PBF
Power MOSFET Selection for Non-Isolated DC/DC Converters
Control FET Special attention has been given to the power losses in the switching elements of the circuit - Q1 and Q2. Power losses in the high side switch Q1, also called the Control FET, are impacted by the Rds(on) of the MOSFET, but these conduction losses are only about one half of the total losses. Power losses in the control switch Q1 are given by; Synchronous FET The power loss equation for Q2 is approximated by;
* Ploss = Pconduction + P + Poutput drive
Ploss = Irms x Rds(on)
+ ( g x Vg x f ) Q
(
2
)
Ploss = Pconduction+ Pswitching+ Pdrive+ Poutput
This can be expanded and approximated by;
Q + oss x Vin x f + (Qrr x Vin x f ) 2
*dissipated primarily in Q1. For the synchronous MOSFET Q2, Rds(on) is an important characteristic; however, once again the importance of gate charge must not be overlooked since it impacts three critical areas. Under light load the MOSFET must still be turned on and off by the control IC so the gate drive losses become much more significant. Secondly, the output charge Qoss and reverse recovery charge Qrr both generate losses that are transfered to Q1 and increase the dissipation in that device. Thirdly, gate charge will impact the MOSFETs' susceptibility to Cdv/dt turn on. The drain of Q2 is connected to the switching node of the converter and therefore sees transitions between ground and Vin. As Q1 turns on and off there is a rate of change of drain voltage dV/dt which is capacitively coupled to the gate of Q2 and can induce a voltage spike on the gate that is sufficient to turn the MOSFET on, resulting in shoot-through current . The ratio of Qgd/Qgs1 must be minimized to reduce the potential for Cdv/dt turn on.
Ploss = (Irms 2 x Rds(on ) ) Qgs 2 Qgd +I x x Vin x f + I x x Vin x f ig ig + (Qg x Vg x f ) + Qoss x Vin x f 2
This simplified loss equation includes the terms Qgs2 and Qoss which are new to Power MOSFET data sheets. Qgs2 is a sub element of traditional gate-source charge that is included in all MOSFET data sheets. The importance of splitting this gate-source charge into two sub elements, Qgs1 and Qgs2, can be seen from Fig 16. Qgs2 indicates the charge that must be supplied by the gate driver between the time that the threshold voltage has been reached and the time the drain current rises to Idmax at which time the drain voltage begins to change. Minimizing Qgs2 is a critical factor in reducing switching losses in Q1. Qoss is the charge that must be supplied to the output capacitance of the MOSFET during every switching cycle. Figure A shows how Qoss is formed by the parallel combination of the voltage dependant (nonlinear) capacitances Cds and Cdg when multiplied by the power supply input buss voltage.
Figure A: Qoss Characteristic
8
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IRF7475PBF
SO-8 Package Outline
Dimensions are shown in millimeters (inches)
D A 5 B
DIM A b INCHES MIN .0532 .013 .0075 .189 .1497 MAX .0688 .0098 .020 .0098 .1968 .1574 MILLIMETERS MIN 1.35 0.10 0.33 0.19 4.80 3.80 MAX 1.75 0.25 0.51 0.25 5.00 4.00
A1 .0040
8 6 E 1
7
6
5 H 0.25 [.010] A
c D E e e1 H K L y
2
3
4
.050 BASIC .025 BASIC .2284 .0099 .016 0 .2440 .0196 .050 8
1.27 BASIC 0.635 BASIC 5.80 0.25 0.40 0 6.20 0.50 1.27 8
6X
e
e1 A C 0.10 [.004] 8X b 0.25 [.010] A1 CAB y
K x 45
8X L 7
8X c
NOT ES : 1. DIMENS IONING & TOLERANCING PER ASME Y14.5M-1994. 2. CONT ROLLING DIMENS ION: MILLIMET ER 3. DIMENS IONS ARE SHOWN IN MILLIMETERS [INCHES]. 4. OUTLINE CONFORMS TO JEDEC OUTLINE MS -012AA. 5 DIMENS ION DOES NOT INCLUDE MOLD PROT RUSIONS . MOLD PROTRUS IONS NOT TO EXCEED 0.15 [.006]. 6 DIMENS ION DOES NOT INCLUDE MOLD PROT RUSIONS . MOLD PROTRUS IONS NOT TO EXCEED 0.25 [.010]. 7 DIMENS ION IS T HE LENGT H OF LEAD FOR SOLDERING TO A S UBST RAT E. 3X 1.27 [.050]
F OOTPRINT 8X 0.72 [.028]
6.46 [.255]
8X 1.78 [.070]
SO-8 Part Marking
EXAMPLE: T HIS IS AN IRF7101 (MOSFET ) DAT E CODE (YWW) P = DES IGNAT ES LEAD-FREE PRODUCT (OPT IONAL) Y = LAS T DIGIT OF T HE YEAR WW = WEEK A = AS S EMBLY S IT E CODE LOT CODE PART NUMBER
INT ERNAT IONAL RECT IFIER LOGO
XXXX F7101
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IRF7475PBF
SO-8 Tape and Reel
Dimensions are shown in millimeters (inches)
TERMINAL NUMBER 1
12.3 ( .484 ) 11.7 ( .461 )
8.1 ( .318 ) 7.9 ( .312 )
FEED DIRECTION
NOTES: 1. CONTROLLING DIMENSION : MILLIMETER. 2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS(INCHES). 3. OUTLINE CONFORMS TO EIA-481 & EIA-541.
330.00 (12.992) MAX.
14.40 ( .566 ) 12.40 ( .488 ) NOTES : 1. CONTROLLING DIMENSION : MILLIMETER. 2. OUTLINE CONFORMS TO EIA-481 & EIA-541.
Notes: Repetitive rating; pulse width limited by max. junction temperature. Starting TJ = 25C, L = 4.7mH R G = 25, IAS = 8.8A. Pulse width 400s; duty cycle 2%.
Data and specifications subject to change without notice. This product has been designed and qualified for the Consumer market. Qualifications Standards can be found on IR's Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information.09/04
10
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